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Circuit Simulation-Driven Analog/RF System-in-Package Webinar Series

Type: Webinar series Date: September 6, 2007 - April 8, 2008 Location: Your desktop Register

Overview



Today's wireless devices manufactures are constantly challenged to pack more functionality into less space in ever-shrinking market windows. To address this demand, analog/RF system-in-package (SiP) modules are becoming one of the fastest growing integration fabrics in the wireless silicon market. However, when designing these complex RF SiP modules, designers are facing challenges that conventional methodologies and technologies just cannot overcome.

In this webinar series, Cadence will take you through these common challenges — presenting a new methodology and integrated technologies that address your key pain points. The webinars will include detailed demonstrations using the latest Cadence SiP RF methodology and technologies that seamlessly integrate with the Cadence® Virtuoso® custom design platform. By attending these webinars, you will learn how driving an RF SiP module implementation from a single top-level schematic (that includes RF/analog die, embedded RF discretes, post-layout parasitic extraction, constraint-driven interconnect, and full SiP tapeout manufacturing preparation) enables full pre- and post-route circuit simulation of the entire SiP.

Archived webinar: Introduction to Circuit Simulation-Driven RF/Analog System-in-Package Design

Topic:	Interfacing With the IC Package Design Team Using Virtuoso and SiP RF Architect
Date:	10/25/07
Time:	9:00 AM Pacific
What you will learn: How the analog/RF IC design team can electronically share design intent with the IC package design team from with their Virtuoso environment How IC logic definitions for top-level SiP schematics can be created automatically How IC footprint definitions for SiP substrate layout can be created automatically
Topic:	Circuit Simulation of Analog/RF ICs with IC Package Interconnect Using Virtuoso ADE and SiP RF
Date:	11/15/07
Time:	9:00 AM Pacific
What you will learn: How to define a single, circuit simulation-capable Virtuoso schematic for a multi-chip system-in-package How to create SiP-level circuit simulation testbenches How package-level interconnect can be included in circuit simulation testbenches How Virtuoso technology can simulate multiple mixed-signal ICs and package structures
Topic:	Designing Off-Chip IC Package/SiP-Level Passive Structures Using Virtuoso and SiP RF Technology
Date:	12/13/07
Time:	9:00 AM Pacific
What you will learn: How SiP substrate-level passive structures can be defined using a top-down schematic and circuit simulation-driven methodology How Virtuoso Pcell technology for simple and complex passive device structures can be implemented at the SiP substrate level
Topic:	Advanced Techniques for IC Package/SiP Parasitic Extraction/Modeling and Backannotation for Circuit Simulation Using Virtuoso ADE and SiP RF
Date:	1/24/08
Time:	9:00 AM Pacific
What you will learn: How actual SiP-level interconnect structures are extracted and annotated into top-level circuit simulation testbenches How SiP layout transmission lines are decomposed and mapped back to initial top-level SiP schematic definition
Topic:	Top-Down Design and Circuit Simulation of Analog/RF Systems-in-Package Using Virtuoso and SiP RF Solutions
Date:	4/8/08
Time:	9:00 AM Pacific
What you will learn: How to capture a top-level circuit simulation-enabled schematic for a multi-chip SiP design How to extract logical and physical SiP views of your chip designs How to define and implement parameterized passive network structures at the SiP substrate level How to set up circuit simulation to simulate critical signal paths across chips and SiP substrate interconnects at the transistor level How to verify LVS and LVL across chip databases and the system-level SiP database

Products featured

• Cadence Virtuoso custom design platform
• Cadence SiP RF technology

Who should attend?

• Analog/RF/Wireless chip design team members
• Advanced IC package designers
• Wireless product/system designers and architects
• Existing Virtuoso custom design platform users

Questions about this event?



Send email to events@cadence.com

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