International Conference on IC Design & Technology - Minatec Grenoble, France; June 2nd – June 4th , 2008

	Call for Papers
	Paper Deadline: February 29th, 2008 International Conference on IC Design & Technology Minatec Grenoble, France; June 2nd – June 4 th, 2008 As IC design & process technology continue to advance for increased performance, lower power, and accelerated time-to-market, the engineering activities, traditionally separated along the boundary of design and process technology, will have difficulties in meeting the shrinking window of product optimization tasks. The International Conference on IC Design & Technology provides a forum for engineers, researchers, scientists, professors and students to cross this boundary through interactions of design and process technology on product development & manufacturing. The unique workshop style of the conference provides an opportunity to technologists and product designers to e xchange breakthrough ideas and collaborate effectively. T wo days of technical presentations and workshops will be preceded by a one-day tutorial program of value to both the expert and the beginner. The venue of 2008 ICICDT will be Minatec® – Maison des Micro et Nano Technologies at Grenoble, France: www.icicdt.org Papers are solicited on: •  Design approaches including system, circuit and EDA to manage power, leakage, process variation, signal integrity, reliability, yield, and manufacturability. •  Advanced VLSI design, including processors, ASICs, memories, analog and mixed-signal circuits. •  System-on-Chip (SoC), System-in-Package (SiP), and IP reuse for fast design closure. •  Advanced materials, advanced metallization, and 3D interconnection as both, novel interconnect scheme for future MPUs and approach for realization of SoCs. •  Process and circuit technology for advanced memories: MRAM, FeRAM, PRAM, Nanocrystal Memory, Flash, etc with emphasis on reliability. •  Advanced transistor structures for bulk, multiple Gate, FDSOI, PDSOI, SSOI, SiGe, etc technologies •  RFCMOS characterization, model, simulation for multiple gate technologies •  New gate materials for adjusting Vt, enhanced mobility & scalability, low leakage, and low power. •  SER, thermal, leakage, PID, reliability, yield, etc effects on advanced transistor structures and circuits. •  Simulation & modeling on advanced process, device & circuit. •  Nanotechnology materials, devices and circuits. •  Emerging IC technologies and circuits crossover such as organic IC's, integrated sensors and integrated actuators. Prospective authors are invited to submit a camera-ready paper of maximum four pages in length, including figures and references. The authors should obtain paper submission guidelines from http://www.ICICDT.org. Accepted/Invited papers will be printed in the proceedings of the conference (also available on CD-ROM). Paper submission deadline is February 29, 2008. Conference Format ICICDT features a popular and unique format structured to maximize face-to-face interaction. An abbreviated synopsis of each paper is presented in a plenary session, following which a workshop-style forum allows for deeper give-and-take communication on an individual basis. Many participants in previous years have commented that this interaction is very rewarding. Contact Information For further general information or assistance in selecting a subject area, please contact: •  Organizing Committee: - General chair Tanay Karnik tanay.karnik@intel.com - Conference chair Amara Amara amara.amara@isep.fr - Executive committee chair Thuy Dao thuy.dao@freescale.com - Local arrangement chair Marc Belleville marc.belleville@cea.fr - Publication chair Thomas Ea thomas.ea@isep.fr - Publicity chair Ingo Aller aller@de.ibm.com - Tutorial chair Ali Keshavarzi ali.keshavarzi@intel.com - Treasurer Christine Nora c.nora@ieee.org - Secretary Jean-Luc Leray jean-luc.leray@cea.fr •  Technical Sub-Committee Chairs: Advanced Memory Devices   - Susumu Shuto susumu.shuto@toshiba.co.jp - Jan Ackaert jan_ackaert@amis.com CAD   - Ruchir Puri ruchir@us.ibm.com DFM/DFT/DFR/DFY   - Keith Bowman keith.a.bowman@intel.com - Jason Stinson jason.stinson@intel.com Low Power   - Toshinari Takayanagi ttoshi@pasemi.com - Geoffrey Yeap gyeap@qualcomm.com SoC/MPSoC/SIP, IC & Platform Design and Process   - Aurangzeb Khan - Dac Pham akkhan@cadence.com dac.pham@freescale.com SER   - Giorgio Cellere giorgio.cellere@ieee.org System Level Technology Assessment   - Phillip Christie phillip.christie@nxp.com Emerging Technology   - Simon Deleonibus simon.deleonibus@cea.fr RF & Analog, Mixed signal   - Didier Belot didier.belot@st.com NBTI & High K Gate Reliability   - Koji Eriguchi eriguchi@kuaero.kyoto-u.ac.jp Advanced Materials   - Chadwin Young Chadwin.young@sematech.org Adv. Transistor Structure, Architecture & Process   - Dong-Won Kim - Arnaud Pouydebasque  timo.kim@samsung.com arnaud.pouydebasque@nxpcrolles.st.com